1. Field of the Invention
The present invention relates to a semiconductor package having a semiconductor constructing body and a method of manufacturing the same.
2. Description of the Related Art
There is conventionally a semiconductor package called a CSP (Chip Size Package). In the CSP, an insulating film is formed on the upper surface of a semiconductor substrate having a plurality of connection pads for external connection. Opening portions are formed in the insulating film in correspondence with the respective connection pads. Interconnections are formed from the upper surfaces of the connection pads exposed through the opening portions to predetermined positions on the upper surface of the insulating film (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2000-195890). In this case, an underlying metal layer is formed on the entire upper surface of the insulating film, including the upper surfaces of the connection pads exposed through the opening portions. Interconnections are formed at predetermined positions on the upper surface of the underlying metal layer by copper electroplating using the underlying metal layer as a plating current path. Unnecessary portions of the underlying metal layer are then removed by etching using the interconnections as a mask so that the underlying metal layer is left only under the interconnections.
In the conventional semiconductor package, as described above, the opening portions are formed in the insulating film in correspondence with the connection pads. The underlying metal layer serving as a plating current path is formed by sputtering or electroless plating, and the interconnections are formed by electroplating. For this reason, the bonding strength between the insulating film and the underlying metal layer is low. In this structure, especially, disconnection readily occurs on the sidewalls of the opening portions. In addition, the reliability of electrical connection between the connection pads and the interconnections is poor.